1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD) protection circuits and more specifically to a power supply RC-based ESD protection clamp circuit.
2. Description of the Related Art
In CMOS (complementary metal-oxide-semiconductor) technologies, a power supply ESD protection clamp provides a low-impedance path from the power supply to the ground supply when an ESD event occurs. An ESD event occurs when a voltage transient having a fast rise and a fast decay time is input to the power or ground supply. However, a power-up event, even a fast power-up event such as may occur when a device is “hot plugged” should not be interpreted as an ESD event.
Conventional RC-based ESD protection circuits rely on an RC-based active NMOSFET (metal-oxide-semiconductor field-effect transistor with N-type channel) as the power supply ESD protection clamp. In contrast with other ESD protection circuits that depend on avalanche junction breakdown phenomena to operate, the RC-based active NMOSFET power supply ESD protection clamp provides a lower turn-on voltage and clamps lower ESD-induced voltage drops during ESD events. FIG. 1 illustrates a conventional RC-based active NMOSFET power supply ESD protection clamp circuit 100, according to the prior art.
To achieve high ESD protection efficiency, the size of the active NMOSFET 110 must be sufficiently large so that the NMOSFET 110 can provide a very low impedance path for the ESD current. To ensure that NMOSFET 110 is fully turned on during ESD events, the RC time constant determined by the resistor R and the capacitor C needs to be greater than the width of a voltage transient that is an ESD event. A typical RC time constant should be greater than 1 us for all process corner variations. Achieving an RC time constant greater than 1 us typically necessitates a large capacitor layout area which is usually larger than the layout area of the NMOSFET 110 in modern CMOS technologies. The large RC time constant layout area negatively impacts the overall die size. As CMOS technologies advance with very thin gate oxide, the larger capacitor in the RC time constant is all associated with significant stand-by power consumption due to a high gate leakage current. Therefore, reducing the die area consumed by the layout of capacitor C used in the power supply ESD protection clamp circuit is desirable.
Further complicating the design of the power supply ESD protection clamp circuit, fast power-up events that occur for hot-plug and power supply switching applications may have voltage ramp times of 1 us or less. Therefore, a RC time constant in the micro-second range may cause the NMOSFET 110 to be falsely triggered during a fast power-up event having a voltage ramp time of less than 10 us. Typical RC-based ESD protection clamp circuits have an allowable power-up slew rate of at least 5V/us or higher to avoid circuit malfunction or silicon damage. However, the maximum allowable power-up slew rate of the RC-based active NMOSFET power supply ESD protection clamp circuit 100 is close to 0.1V/us due to having a high RC time constant.
Accordingly, what is needed in the art is a power supply RC-based ESD protection clamp circuit that uses a resistor and capacitor having a smaller RC time constant, and reduced layout area that also has a very high allowable power-up voltage slew rate.